Contact

Program Committee

  • Ahmed Jerraya, CEA, FR
  • Alex Bartzas, NTUA, GR
  • Alex Orailoglu, UCSD, US
  • Carlo Galuzzi, TU Delft, NL
  • Cedric Bastoul, U Paris-Sud, FR
  • Chantal Ykman-Couvreur, IMEC, BE
  • Cristina Silvano, POLIMI, IT
  • Erven Rohou, INRIA, FR
  • Eugenio Villar, UC, ES
  • Francois Pacull, CEA, FR
  • Georgios Sirakoulis, DUTH, GR
  • Gianluca Palermo, POLIMI, IT
  • Holger Blume, U Hannover, DE
  • Joao Cardoso, UP, PT
  • Kari Tiensyrja, VTT, FI
  • Kees Goossens, TUE, NL
  • Lars Bauer, KIT, DE
  • Leandro Indrusiak, U York, UK
  • Leonel Sousa, INESC, PT
  • Massimo Poncino, POLITO, IT
  • Mladen Berekovic, TUB, DE
  • Pedro Diniz, USC, US
  • Praveen Raghavan, IMEC, BE
  • Rainer Buchty, TUB, DE
  • Ramon Canal, UPC, ES
  • Roel Wuyts, IMEC and KUL, BE
  • Sander Stuijk, TUE, NL
  • Sotirios Xydis, POLIMI, IT
  • Stavros Tripakis, UC Berkeley, US
  • Stefano Crespi, POLIMI, IT
  • Thierry Lepley, ST, FR
  • Tulika Mitra, NU Singapore, SG
  • William Fornaciari, POLIMI, IT
  • Yiannis Papaefstathiou, TUC, GR

Berlin, Germany, January 23, 2013

Co-located with HiPEAC 2013


The PARMA Workshop is jointly supported by the
2PARMA project
funded by the FP7-ICT Programme
under the Objective Computing Systems
http://www.2parma.eu/

Workshop Final Program


14:00 Opening address

  • Dimitrios Soudris

14:10 Keynote address: Dynamic parallelism in the Kepler architecture

  • Luke Durant, NVIDIA

  • Abstract: Dynamic Parallelism is a new programming model feature in CUDA that enables GPU kernels to create new GPU kernels, no longer requiring the CPU to make all decisions about the work to needed to run on the GPU. The Kepler architecture is the first GPU architecture with enough flexibility to enable interesting new software runtimes. One such software runtime has been developed to run on the GPU and enable the APIs and language semantics necessary for Dynamic Parallelism. This talk provides an overview of the Dynamic Parallelism programming model and runtime system.

  • Bio: Luke Durant is a senior engineer in CUDA software at NVIDIA, where he is currently the CUDA chips lead for the Maxwell architecture. Prior to his current role, Luke was the lead engineer for the Dynamic Parallelism feature introduced with the Kepler architecture. Luke graduated from the California Institute of Technology with a B.Sc. in Computer Science prior to joining NVIDIA in 2010.

14:50 Session 1


  • Parallel SAT solver Based on the Galois System
    Tatjana Djokic, Stanisa Dautovic

    Solving Combinatorial Optimisation Problems on Many-core Platforms
    Peng Wang, Yuet Ming Lam, Kuen Hung Tsoi, Wayne Luk

    A Framework for Supporting Parallel Application Placement onto Reconfigurable Platforms
    Dionysios Diamantopoulos, Kostas Siozios, Sotirios Xydis, Dimitrios Soudris

    Sync-aware Low Leakage Register File for GPUs
    Ali Jooya, Amirali Baniasadi

16:00 Coffee break - Poster session


16:30 Session 2


  • Towards Power Efficiency on Task-Based, Decoupled Access-Execute Models
    Konstantinos Koukos, David Black-Schaffer, Vasileios Spiliopoulos, Stefanos Kaxiras

    Resource-aware task scheduling
    Martin Tillenius, Elisabeth Larsson, Rosa M. Badia, Xavier Martorell

    Fine-Grain Conflict Management for Hardware Transactional Memory Systems Employing Eager Version Management
    Shoichiro HORIBA, Hiroki ASAI, Masamichi ETO, Tomoaki TSUMURA, Hiroshi MATSUO

    Exploiting Linux Control Groups for Effective Run-time Resource Management
    Patrick Bellasi, Giuseppe Massari, William Fornaciari

    Adaptive memory management for applications of highly-varying runtime requirements
    Ioannis Koutras, Alexandros Bartzas, Dimitrios Soudris

17:50 NVIDIA Best Paper Award, Closing

  • Giovanni Agosta